The arrival of the information age has created a demand for light-weight, thin, and fast-response displays, initiating active research and development of organic EL (Electro Luminescence) displays and FED (Field Emission Device). The organic EL display is also known as an organic LED, which is expected to be used in the areas of portable terminal devices by virtue of its self-emitting property and low voltage operation and low power consumption.
The organic EL display is available in two types: the passive-matrix type and the active-matrix type, of which the latter is expected to be the main stream scheme in the future. The driving method of the organic EL display is either voltage-controlled or current-controlled, wherein each type of driving method uses either digital driving or analog driving. That is, the driving method of the organic EL display can be divided into four major driving modes.
In the organic EL display, even a slight voltage change causes a large luminance fluctuation, owing to the non-linear luminance-voltage characteristics of the organic EL element. Further, since its characteristic curve easily fluctuates in response to a change in drive time or ambient temperature of the element, it is very difficult to suppress luminance variations by a voltage-controlled driving method. On the other hand, the luminance-current characteristics of the organic EL element have a proportional relationship, and the influence of ambient temperature is small. It is therefore easier to control luminance by current. Indeed, the current-control is a more preferable method of driving the organic EL display.
The TFT (Thin Film Transistor), which is a switching element for the pixel circuit and driving circuit, is realized by amorphous silicon, low-temperature polysilicon, or CG (Continuous Grain) silicon. Generally, the low-temperature polysilicon or CG silicon is used for the TFT since they can accommodate large currents that are sufficient to provide a relatively large current level required for driving the organic EL element. The low-temperature polysilicon and CG silicon are also preferable as TFT materials in terms of display cost and display size, since they enable peripheral circuits to be formed on the same glass material where the display elements are formed.
One example of an organic EL display using the current-controlled driving mode and in which peripheral circuits are incorporated on the glass substrate is a current-driver integrated organic EL display disclosed in Japanese Publication for Unexamined Patent Publication No. 195812/2003 (Tokukai 2003-195812, published on Jul. 9, 2003), as shown in FIG. 19.
In a data driving circuit 100 shown in FIG. 19, an externally supplied digital image data signal is fed to a data latch 102 at a generated timing of a shift register 101, and data of one scan line (digital image data signal) is stored in a line latch 103. The stored data is then converted into a 6-bit analog signal in a voltage/current converting circuit 104, and is outputted to data lines S1 through S120 of a display panel 109 through a 1-to-2 selector 106.
The voltage/current converting circuit 104 refers to 6-bit reference currents Is through Is×32 supplied from a reference current source 107 and resets (refreshes) its output value, so as to convert the output 6-bit digital image data signal of the line latch 103 into the 6-bit analog signal for output. The shift register 105 supplies timings of applying the reference currents. This is carried out in synchronism with the period in which the voltage/current converting circuit 104 does not output the analog signal.
A gate driving circuit 108 receives a select-scan line signal from outside, and selects scan lines G1 through G136 of the display panel 109 in a predetermined order for pulse driving.
FIG. 20 illustrates details of the voltage/current converting circuit 104 shown in FIG. 19.
The voltage/current converting circuit 104 includes sets of 6-bit DCC circuits 201, each having six voltage/current converting circuits (1-bit DCC) of a current-copier type. Each DCC circuit 201 holds (stores) a reference 6-bit current value in its 1-bit DCC capacitor, and either outputs or does not output the stored current value according to each bit of the externally supplied 6-bit digital image data signal. The stored current value is outputted when the driving switching element is ON, and is not outputted when it is OFF.
Further, in the DCC circuit 201, an A/B selector 204 selects one of the outputs respectively produced in a 6-bit DCC-A202 and a 6-bit DCC-B203 making up a pair. The selected output is supplied to data lines Sj via the 1-to-2 selector 106. That is, the voltage/current converting circuit 104 includes sixty DCC circuits 201, each having a pair of 6-bit DCC-A202 and 6-bit DCC-B203.
Here, the data driving circuit 100 is configured for a monochromatic 6-bit input signal, and only ⅓ of the structure is shown for an RGB full color display device, for example (FIG. 19 only shows a configuration for red (R)).
FIG. 21 is a timing chart representing operations of the data driving circuit 100.
As shown in FIG. 21, one frame includes recurrently alternating frame A and frame B.
In frame A, the signal output to the pixel circuits is controlled such that the outputs D1-B1 through D1-B6 of the line latch 103 are all OFF, and such that only 6-bit data DCC-A1 through DCC-A6 are supplied to the 1-to-2 selector 106 by the A/B selector 204. Further, in frame A, the shift register 105 outputs timing signals MSB1 through MSB60 of a high (H) level as current memory pulses. Accordingly, only the 6-bit DCC-B203 is refreshed in turn by the timing signals MSB1 through MSB60. Here, only the current value (image data signal) stored in the 6-bit DCC-A202 is outputted according to the 6-bit data D1-A1 through D1-A6 supplied from the line latch 103 (Iout1).
Conversely, in frame B, the shift register 105 outputs timing signals MSA1 through MSA60 of a high (H) level as current memory pulses. Accordingly, only the 6-bit DCC-A202 is refreshed in turn by the timing signals MSA1 through MSA60. Here, only the current value (image data signal) stored in the 6-bit DCC-B203 is outputted according to the 6-bit data D1-B1 through D1-B6 supplied from the line latch 103 (Iout1).
In frame A or frame B, the output period of the supplied signal to the pixel circuits is divided into two parts. In other words, one horizontal scan period for selecting and scanning a single gate line is divided into two periods. The 1-to-2 selectors 106 are switched in synchronism with a switch timing of these two periods.
In this way, in the first half (1st H) of one horizontal scan period, the signal is supplied to only those pixel circuits connected to the odd-numbered or even-numbered data lines of the selected scan lines. In the second half (2nd H) of the horizontal scan period, the signal is supplied to the pixel circuits connected to the other half of the data lines. In effect, in the configuration shown in FIG. 20, the 6-bit DCC201 with a pair of 6-bit DCC-A202 and 6-bit DCC-B203 is used for each data line to operate the display device.
FIG. 22(a) through FIG. 22(d) show an operation of a 1-bit DCC205, which is a basic unit of the data driving circuit 100. As shown in FIG. 22(a), the 1-bit DCC205 includes a current memory signal line MSj, a digital signal line Dj, a reference current signal line SCLn, a signal output line Ioutj, switching elements SW101 through SW103, a switching element SWD101 across which a reference current Is×n is flown, and a capacitor Cs101. The source-drain voltage of the switching element SWD101 corresponding to the reference current Is×n is held in the capacitor Cs101. Using this operation of the switching element SWD101 and the capacitor Cs101, the 1-bit DCC205 holds the current value Is×n, which is the output value of the switching element SWD101.
When the current memory signal line MSj and the digital signal line Dj become high potential and low potential, respectively, the switching elements SW101 and SW102 are turned on, and the switching element SW103 is turned off. In response, as shown in FIG. 22(b), the reference current Is×n flows to ground through the reference current signal line SCLn and the switching elements SW101 and SWD101. Simultaneously, the capacitor Cs101 is charged through the switching element SW102 so as to obtain a gate-source voltage that is in accordance with the reference current.
Then, as shown in FIG. 22(c), the current memory signal line MSj is brought to low potential (L) with the digital signal line Dj held at low potential (L). This turns off the switching elements SW101 and SW102. As a result, the capacitor Cs101 holds a gate-source voltage that causes the switching element SWD101 to flow the reference current. Finally, as shown in FIG. 22(d), the digital signal line Dj is brought to high potential (H) with the current memory signal line MSj held at low potential (L). This turns on only the switching element SW103. As a result, the same current value stored in the capacitor Cs101 is supplied to the output line Ioutj connected to the pixel circuits.
The state shown in FIG. 22(b) represents the DCC refresh operation. FIG. 22(c) represents a state in which the current value is held, or “OFF (no emission)” is selected with a digital signal of a corresponding bit. FIG. 22(d) represents a state in which “ON (emission)” is selected with a digital signal of a corresponding bit.
It should be noted here that the pixel circuit used in the display device of the current-controlled analog driving mode proposed in Publication (1) below is described in detail in Publication (2). Accordingly, no explanation will be given therefor.    (1) K. Abe et al. “A Poly-Si TFT 6-bit Current Data Driver for Active Matrix Organic Light Emitting Diode Displays”, EuroDisplay 2002, pp. 279-282.    (2) M. Shimoda et al. “New Pixel-Driving Scheme with Data-Line Pre-Charge Function for Active Matrix organic Light Emitting Diode Displays”, IDW '02, pp. 239-242.    (3) R. Hattori, “Data-Line Driver circuits for Current-ProgrammeDCCtive-Matrix OLED Based on Poly-Si TFTs”, AM-LCD2002, Jul. 10-12, 2002, pp. 17-20.
The data driving circuit of Publication (1) realizes the current-controlled analog driving for 6-bit gradation display for each color of RGB. This is realized by the voltage/current converting circuit that uses pairs of 6-bit DCCs which are provided in a number corresponding to the number of 6-bit display gradations, wherein the basic unit of the 6-bit DCCs is a 1-bit DCC that includes four switching elements and a single charge-holding-element.
However, in the driving methods proposed in Publications (1) and (2), the pixel signal stored in the data driving circuit is not a voltage but is a current, and the reference current source for the stored current is provided one for each bit. Accordingly, the 1-bit DCCs, which are provided in parallel, cannot store the current at the same time. In order to store current at the same time, a plurality of reference current sources needs to be provided for each bit. However, such a structure is not practical since it may cause luminance variations in the display device. It is therefore preferable that a single reference current source be provided for each bit, and that the 1-bit DCCs be individually refreshed at different timings.
As described in Publication (3), the time required for the 1-bit DCC to store a current is on the order of several microseconds, though it depends on the characteristics of the electro-optic element or switching element used in the display device. Publication (3) also describes that more time is needed to store the current as its current value becomes smaller.
Details of Publication (1) are disclosed in Japanese Unexamined Patent Publication No. 195812/2003 (Tokukai 2003-195812).
As described above, the current driving circuit disclosed in Publication (1) includes two 6-bit DCCs 201 (6-bit DCC-A202 and 6-bit DCC-B203) for each data line. The current driving circuit operates such that the 6-bit DCC-B203 stores a current while the 6-bit DCC-A202 outputs s signal to the pixels. Conversely, the 6-bit DCC-A202 stores a current during the output period of the 6-bit DCC-B203. With this operation of the current driving circuit, the 1-bit DCC can store a current only when the switching element SW3 of the 1-bit DCC is OFF, i.e., when all of the digital signal lines Dj are at low potential (all the bits of the 6-bit data D-A1 through D-A6 or D-B1 through D-B6 are “0”), as described above. Further, as noted above, the 1-bit DCC requires some time to store current.
With the 6-bit DCC-A202 or 6-bit DCC-B203 alone, a low-potential state for all the digital image data signals is attained only during the scan period of an nth line and (n+1)th line, i.e., during the non-output period of the image data signals from the DCC circuit 201 to the pixel circuits. In common display devices, such a low-potential period is only about several times longer than a required refresh period for the 1-bit DCC described in Publication (3), and is insufficient to refresh all the 1-bit DCCs in the display device. The 6-bit DCC-A202 and 6-bit DCC-B203 are used in pairs in order to provide enough of a refresh period for the 1-bit DCC.
Further, in the driver-integrated display device incorporating an electro-optic element, low-temperature polysilicon or CG silicon needs to be used as a semiconductor material for the TFT provided as a switching element. For this reason, the element characteristics tend to vary even between adjacent elements. Such variations of TFT characteristics can be suppressed when the size of TFT is increased to some extent. If the size of TFT were to be increased in the circuit disclosed in Publication (1) for example, then the circuit would require a considerably large area. Further, since the number of required TFT elements is large, even a defect in a single element can easily lead to errors in the entire operation of the circuit.
As described so far, a problem of the conventional techniques is the inability of the 1-bit DCCs to simultaneously store the current. In order to overcome this drawback, many conventional display devices for carrying out n-bit gradation display use a method of operation in which a pair of n-bit DCCs, which is provided for each data line, operates alternately in two operation modes in frame A and frame B provided in one frame period. In frame A, one of the n-bit DCC outputs current while the other stores current. In frame B, this operation of the n-bit DCCs is reversed. A drawback of this method, however, is that it requires a considerably large data driving circuit, because a pair of n-bit DCCs is required for each data line. Another drawback is that the n-bit DCCs need to be connected to the data line via a switching circuit (A/B selector 204), so as to switch the n-bit DCCs connected to the data line between frame A and frame B.
Further, in the driving circuit disclosed in Publication (1), the n-bit DCC installed in the device is provided one for each data line. This structure requires an additional 1-to-2 selector circuit for switching two data lines to be connected to the DCC.
In this manner, in order to send image data signals to the pixel circuits, one horizontal scan period is divided and the 1-to-2 selector or A/B selector is used to switch the n-bit DCCs connected to a single data line. This increases the operating frequency of the data driving circuit and thereby increases power consumption.
Further, dividing one horizontal scan period reduces the write time of the image data signals to the pixel circuits. As with the 1-bit DCC in the data driving circuit, the pixel circuits require a longer write time for smaller current. It is therefore not preferable to reduce the horizontal scan period.
As described above, the method in which two n-bit DCCs making up a pair are alternately operated for the operations of refreshing and signal output is disadvantageous in terms of miniaturization and whole power consumption of the device. Further, the probability of circuit defect increases as the size of the driving circuit is increased by the provision of complicated circuits such as the 1-bit DCCs, making it difficult to ensure reliability and productivity at the same time for the display device.